The present invention relates in general to semiconductor device fabrication methods and resulting structures. More specifically, the present invention relates to fabrication methods and resulting structures for preventing threshold voltage (Vt) variability in a stacked nanosheet structure.
In contemporary semiconductor device fabrication processes a large number of semiconductor devices, such as field effect transistors (FETs), are fabricated on a single wafer. Some non-planar device architectures, such as nanosheet FETs, provide increased device density and some increased performance over lateral devices. In nanosheet FETs, in contrast to conventional FETs, the gate stack wraps around the full perimeter of each nanosheet, enabling fuller depletion in the channel region, and reducing short-channel effects due to steeper subthreshold swing (SS) and smaller drain induced barrier lowering (DIBL). The wrap-around gate structures and source/drain contacts used in nanosheet devices also enable greater management of leakage current and parasitic capacitance in the active regions, even as drive currents increase.